Current State

Snapshot

Stable Phase 0 — Foundation: complete
Stable Phase 1 — Core Platform: complete
Stable Phase 1.5 — Public Web Product: complete
Stable Phase 2 — Single Provider: complete
Stable Phase 2.5 — Provider Generalization: complete
New Phase 3 — Core Memory Substrate: in progress (Track C)
New Phase 3.5 — Extraction & Context Assembly: planned
New Phase 4 — Operator Platform & Multi-Provider: planned
New Phase 4.5 — Intelligence Layer: planned
New Phase 5 — Advanced Retrieval & Graph Memory: planned

Last updated: 2026-08-27
Branch: feature/m3-c-3-temporal-conflict
Current focus: Close out Track C planning gaps on #618, then 3.C.5 Write-path persistence
Completed (recent): 3.C.3 temporal conflict (ADR-0056); 3.C.2 exact + near-dup (#614); 3.C.1 PII (#604); 3.2.1 VectorStore; 3.1.1 schema expand

Roadmap hub

Live phase cards and milestone progress.

3.C.5 Write orchestration

Steps 7–9 + HTTP write + escalations (ADR-0057).

3.C.3 Temporal conflict

Interval-overlap-first conflict (ADR-0056).

Architecture decisions

Accepted ADRs through ADR-0057.

Shipped Since Last Update

Phase 3 Track C 3.C.3: Interval-overlap-first conflict + ADR-0056 (merging on #618)
Track C planning closeout: ADR-0057 + milestone 3.C.5 owns steps 7–9; escalations deferred to #620
Phase 3 Track C 3.C.2: Exact SHA-256 + near-dup via VectorStore (ADR-0055)
Phase 3 Track C 3.C.1: Presidio PII detect/redact + write Stage seam (ADR-0054)
Phase 3 Track B complete: VectorStore ABC + PgVectorStore, scoring v2, embedder HTTP client (ADR-0053)
Phase 3 Track A complete: 000017_memory_schema_v2_expand (ADR-0052)

What Ships Today

Merge #618 (3.C.3 + Track C closeout).
Implement 3.C.5 (#620).
Then 3.C.4 multi-label, then Track D.

See Phase 3.