Phase 3 — Tracks

Track A — Schema & Migrations

Memory schema with temporal validity, multi-label categories, and HNSW-ready vector columns. Schema details are a planning baseline and may be refined during implementation.

Preferred sequencing within track: single foundation milestone; blocks Tracks B–D. Status: 3.1.1 completed (ADR-0052 / 000017).

3.1.1 — Memory Schema v2 (completed)

Track B — Vector Store & Embedding

Pluggable vector store interface with pgvector HNSW as the starting backend preference (replacing the earlier IVFFlat plan). Alternatives can be investigated if latency/recall measurements require it.

Preferred sequencing within track: depends on Track A schema.

3.2.1 — Vector Store Interface & pgvector HNSW

Track C — Write Pipeline

Memory write pipeline stages: validate → PII detect/redact → dedup → embed → near-dup → conflict detect → DB write → cache update → index. Stage order is the preferred starting sequence and can be adjusted after integration testing.

Step	Stage	Owner
1	validate	Seam from 3.C.1
2	PII detect/redact	3.C.1 (ADR-0054)
3	exact dedup	3.C.2 (ADR-0055)
4	embed	Track B client / pipeline
5	near-dup	3.C.2 (ADR-0055)
6	conflict detect	3.C.3 (ADR-0056)
7	DB write (+ apply supersessions / escalations)	3.C.5 (ADR-0057)
8	cache update	3.C.5 (write-time; 3.D.3 is read hot cache)
9	index / vector upsert	3.C.5

Multi-label classification (3.C.4) is write-path logic that runs at insert time and therefore follows 3.C.5.

Preferred sequencing within track: 3.C.1 → 3.C.2 → 3.C.3 → 3.C.5 → 3.C.4 after Tracks A/B.

Track D — Read/Ranking Pipeline

Semantic search read path, composite scoring with category-conditional decay, and Redis sorted-set hot cache.

Preferred sequencing within track: 3.D.1 → 3.D.2 → 3.D.3 after Track B.

Track E — Exit Gate

Security integration suite, E2E lifecycle test, retrieval-quality benchmark, ADR consolidation, and exit audit.

Preferred sequencing within track: 3.E.1 → 3.E.2 → 3.E.3 → 3.E.4 → 3.E.5 after Tracks A–D.